Memory Hakim Weatherspoon CS 3410, Spring 2012 Computer

Memory Hakim Weatherspoon CS 3410, Spring 2012 Computer

Memory Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See: P&H Appendix C.8, C.9 Big Picture: Building a Processor memory inst +4 register file +4 =? PC control offset new pc alu

cmp addr din dout memory target imm extend A Single cycle processor 2 Goals for today Review Finite State Machines Memory Register Files Tri-state devices

SRAM (Static RAMrandom access memory) DRAM (Dynamic RAM) 3 Example: Digital Door Lock Digital Door Lock Inputs: keycodes from keypad clock Outputs: unlock signal display how many keys pressed so far 4 Door Lock: Inputs Assumptions: signals are synchronized to clock Password is B-A-B K A B K A B Meaning 0 0 0 (no key) 1 1 0 A pressed 1 0 1 B pressed

5 Door Lock: Outputs Assumptions: High pulse on U unlocks door D3D2D1D0 4 LED 8 dec U 6 Door Lock: Simplified State Diagram G1 1 A B G2 2

else B else G3 3, U any Idle 0 else any B1 1 else B2 2

else B3 3 7 Door Lock: Simplified State Diagram G1 1 A else B G2 2 else B G3 3, U

any Idle 0 else else B1 1 else B2 2 8 Door Lock: Simplified State Diagram G1 1

A else B G2 2 else Idle 0 else else B1 1 else B2 2 B

Cur. State Idle G1 G2 G3 B1 B2 G3 3, U any Output 0 1 2 3, U 1 2 9 Door Lock: Simplified State Diagram G1

1 A else B Idle 0 else else B1 1 else Cur. State G2Idle B 2Idle Idle else G1 G1 G1 G2

G2 G2 B2 G3 2 B1 B1 B2 B2 Input Next State G3 Idle 3, U B G1 A B1 any G1 A G2 B B2 B2 B G3 A Idle

any Idle B1 K B2 B2 K Idle 10 State Table Encoding SCur. SState S0 D 3 2 1 0 Idle 0 0 0 0 G1 0 1 0 0 G2 1 0 0 0 G3 1 1 0 1 B1 0 0 0 1 B2

0 1 0 State K A B D3D2D1D 0 0 Idle 0 0 U 1 G1 1 0 DOutput 2 D1 D0 0 0 0 0 0 1 0 1 0 2 1 0 03, 1 U1 0 1 0 1 0 2 1 0 U

0 0 0 1 0 0 S2 S1 8 S0 4Meaning dec 0 0 0(no key) 0 1 A0pressed R G2 0 1 1 0 1 B pressed 0 P G3 0 1 1 Q B1 1 0 0 B2 1

0 1 S2 SState Cur. 1 S0 0 Idle 0 0 0 Idle 0 0 0 Idle 0 0 0 G1 0 1 0 G1 0 1 0 G1 0 1 0 G2 1 0 0 G2 1 0 0 G2 1 0 0 G3 1 1 1 B1

0 0 1 B1 0 0 1 B2 0 1 1 B2 0 1 K Input A B 0 0 0 1 B 0 1 1 A 1 0 0 0 0 1 A 1 0 1 B

0 1 0 0 0 1 B 0 1 1 A 1 0 x any x x 0 0 0 1 K x x 0 0 0 1 K

x x S Next 2 SState 1 S0 0 Idle 0 0 0 G1 0 1 1 B1 0 0 0 G1 0 1 0 G2 1 0 1 B2 0 1 0 B2 1 0 0 G3 1 1 0 Idle 0 0 0 Idle 0 0 1 B1 0 0

1 B2 0 1 1 B2 0 1 0 Idle 0 0 11 3bit Reg S2-0 D3-0 U 4 dec Door Lock: Implementation clk S2-0 A B S2-0

C Strategy: (1) Draw a state diagram (e.g. Moore Machine) (2) Write output and next-state tables (3) Encode states, inputs, and outputs as bits (4) Determine logic equations for next state and outputs 12 Administrivia Make sure partner in same Lab Section this week Lab2 is out Due in one week, next Monday, start early Work alone But, use your resources Lab Section, Piazza.com, Office Hours, Homework Help Session, Class notes, book, Sections, CSUGLab No Homework this week 13 Administrivia Check online syllabus/schedule http://www.cs.cornell.edu/Courses/CS3410/2012sp/schedule.html Slides and Reading for lectures Office Hours Homework and Programming Assignments Prelims (in evenings): Tuesday, February 28th

Thursday, March 29th Thursday, April 26th Schedule is subject to change 14 Collaboration, Late, Re-grading Policies Black Board Collaboration Policy Can discuss approach together on a black board Leave and write up solution independently Do not copy solutions Late Policy Each person has a total of four slip days Max of two slip days for any individual assignment Slip days deducted first for any late assignment, cannot selectively apply slip days For projects, slip days are deducted from all partners 20% deducted per day late after slip days are exhausted Regrade policy Submit written request to lead TA, and lead TA will pick a different grader Submit another written request, lead TA will regrade directly Submit yet another written request for professor to regrade.

15 Goals for today Review Finite State Machines Memory Register Files Tri-state devices SRAM (Static RAMrandom access memory) DRAM (Dynamic RAM) 16 Register File Register File N read/write registers Indexed by register number QA 32

Implementation: D flip flops to store bits Decoder for each write port Mux for each read port DW Dual-Read-Port Single-Write-Port Q B 32 x 32 Register File W 1 32 32 R W RA R B 5 5 5 17 Register File Register File

N read/write registers Indexed by register number QA 32 Implementation: D flip flops to store bits Decoder for each write port Mux for each read port DW Dual-Read-Port Single-Write-Port Q B 32 x 32 Register File W 1 32 32 R W RA R B 5 5

5 18 Register File Register File N read/write registers Indexed by register number QA 32 Implementation: D flip flops to store bits Decoder for each write port Mux for each read port DW Dual-Read-Port Single-Write-Port Q B 32 x 32 Register File W 1 32

32 R W RA R B 5 5 5 19 Tradeoffs Register File tradeoffs + Very fast (a few gate delays for both read and write) + Adding extra ports is straightforward Doesnt scale 20 Building Large Memories Need a shared bus (or shared bit line) Many FFs/outputs/etc. connected to single wire Only one output drives the bus at a time 21 Tri-State Devices Tri-State Buffers

E D E 0 0 1 1 Q D Q 0 z 1 z 0 0 1 1 E D Vdd D Q Gnd 22 Tri-State Devices Tri-State Buffers

E D E 0 0 1 1 Q D Q 0 z 1 z 0 0 1 1 E D Vdd D Q Gnd 23 Shared Bus D0 S0

D1 S1 D2 S2 D3 S3 D1023 S1023 shared line 24 SRAM Static RAM (SRAM) Essentially just SR Latches + tri-states buffers 25 SRAM Chip 26 row decoder SRAM Chip A21-10 A9-0

column selector, sense amp, and I/O circuits Shared Data Bus CS R/W 27 Typical SRAM Cell B bit line SRAM Cell word line B Each cell stores one bit, and requires 4 8 transistors (6 is typical) Read: pre-charge B and B to Vdd/2 pull word line high cell pulls B or B low, sense amp detects voltage difference Write: pull word line high drive B and B to flip cell

28 SRAM Modules and Arrays 1M x 4 SRAM 1M x 4 SRAM 1M x 4 SRAM 1M x 4 SRAM R/W A21-0 CS msb Bank 2 lsb CS Bank 3

CS Bank 4 CS 29 SRAM Summary SRAM A few transistors (~6) per cell Used for working memory (caches) But for even higher density 30 Dynamic-RAM (DRAM) Data values require constant refresh bit line Dynamic RAM: DRAM word line Capacitor Gnd 31

DRAM vs. SRAM Single transistor vs. many gates Denser, cheaper ($30/1GB vs. $30/2MB) But more complicated, and has analog sensing Also needs refresh Read and write back every few milliseconds Organized in 2D grid, so can do rows at a time Chip can do refresh internally Hence slower and energy inefficient 32 Memory Register File tradeoffs + + Very fast (a few gate delays for both read and write) Adding extra ports is straightforward

Expensive, doesnt scale Volatile Volatile Memory alternatives: SRAM, DRAM, Slower + Cheaper, and scales well Volatile Non-Volatile Memory (NV-RAM): Flash, EEPROM, + Scales well Limited lifetime; degrades after 100000 to 1M writes 33 Summary We now have enough building blocks to build machines that can perform non-trivial computational tasks Register File: Tens of words of working memory SRAM: Millions of words of working memory DRAM: Billions of words of working memory NVRAM: long term storage (usb fob, solid state disks, BIOS, ) Next time we will build a simple processor! 34

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