CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/

CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/

CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ FSM as an Arbiter Circuit CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

Administrative Stuff Homework 11 is out It is due on Monday Dec 1, 2014 @ 4pm Administrative Stuff Final Project (7% of your grade) Read the instructions in the e-mail that I sent you. Let me know if you did not get that e-mail. Also, posted on the class web page (Labs section) This is your lab for the next two weeks This is due during your last lab (in two weeks)

Sample E-mail Hello TAs, I decided to pick problem number x for my final project in CprE 281. Thanks, [your name] Arbiter Circuit Goal Design a machine that controls access by several devices to a shared resource

The resource can be used by only one device at a time Any changes can occur only on the positive edge of the clock signal Each device provides one input the the FSM, which is called a request The FSM produces one output for each device, which is called a grant Goal The requests from the devices are prioritized If two requests are active at the same time, then only the device with the highest priority will be given

access to the shared resource After a device is done with the shared resource, it must make its request signal equal to 0. If there are no outstanding requests, then the FSM stays in an Idle state Conceptual Diagram Request1 Grant1 Device 1

Request2 Arbiter Grant2 Device 2 Request3 Grant3 Device 3

Shared resource Conceptual Diagram Request1 Grant1 Device 1 Request2 Arbiter

Grant2 Device 2 Shared resource Request3 Grant3 Device 3

Request (r) Grant (g) [ Figure 9.20 from the textbook ] State diagram for the arbiter 000 Reset Idle 0xx 1xx

gnt1g1 =1 x0x 1xx 01x gnt2g2 =1 xx0 x1x

001 gnt3g3 =1 xx1 [ Figure 6.72 from the textbook ] State diagram for the arbiter 000 Reset Idle

0xx Highest Priority Device 1xx gnt1g1 =1 x0x 1xx 01x

gnt2g2 =1 xx0 x1x gnt3g3 =1 xx1 001 State diagram for the arbiter 000

Reset Idle 0xx Highest Priority Device 1xx gnt1g1 =1 x0x

1xx 01x gnt2g2 =1 Lowest Priority Device xx0 x1x gnt3g3 =1 xx1

001 State diagram for the arbiter The three request bits 000 Reset r 1 r 2 r3

Idle 0xx 1xx gnt1g1 =1 x0x 1xx 01x

gnt2g2 =1 xx0 x1x gnt3g3 =1 xx1 001 State diagram for the arbiter Each device must release the resource

after it is done using it 000 Reset Idle 0xx 1xx gnt1g1 =1 x0x

1xx 01x gnt2g2 =1 xx0 x1x gnt3g3 =1 xx1

001 Alternative style of state diagram for the arbiter r1 r2 r3 Reset Idle r1 r1 gnt1g1 =1

r2 r1 r1 r2 gnt2g2 =1 r3 r2 r1 r2 r3

gnt3g3 =1 r3 [ Figure 6.73 from the textbook ] Let's look at a simpler example with only two devices that need to use the shared resource State diagram for the simpler arbiter 00

Reset Idle 0x 1x gnt1g1 =1 x0 1x gnt2g2 =1 x1

01 State diagram for the arbiter circuit State Table State-Assigned Table Output Expressions Next State Expressions

Circuit Diagram Questions? THE END

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