Reconfigurable Computing Methods for Increasing Portability and Productivity

Reconfigurable Computing Methods for Increasing Portability and Productivity

Reconfigurable Computing Methods for Increasing Portability and Productivity Joe Kimbrell James MacKinnon Jacob Stewart 1/63 Paper Selection Kirchgessner, R.; George, A.D.; Lam, H., Reconfigurable computing middleware for application portability and productivity, Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on ,

vol., no., pp.211,218, 5-7 June 2013 doi: 10.1109/ASAP.2013.6567577 Vuletic, M.; Pozzi, L.; Ienne, P., Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing, Application-Specific Systems, Architectures and Processors, 2004. Proceedings. 15th IEEE International Conference on , vol., no., pp. 339,351, 27-29 Sept. 2004 doi: 10.1109/ASAP.2004.1342483 2/63 Reconfigurable Computing Middleware for Application Portability and Productivity

3/63 Introduction Advantages of reconfigurable devices Flexibility for application specific tasks High performance, low power Difficulties of using reconfigurable devices Lack of standardization between platforms Difficult to port code Vendor specific cores

4/63 Possible Solution - HLS High-level synthesis (HLS) Reduce the difficulties of FPGA development Encounter the same lack of portability HLS tool must support various platforms Impulse-C: per-platform support packages ROCCC: per-platform application cores

FPGA device development outpaces tool development HLS tools must make assumptions which decreases efficiency of generated core 5/63 RC Middleware (RCMW) Designed to enable more portability User specifies required resources and interfaces via XML at design time

Including number, type, size, and data types of each resource RC Middleware toolset creates a portable hardware and software interface Portability is no longer a concern as the interface can be generated for many different devices 6/63

Related Work RCMW is a complementary technology to other FPGA abstraction methods Intermediate Fabrics coarse grained logic blocks that increase FPGA compile times FPGA-on-FPGA overlays provides compatibility between devices without requiring bitfile recompilation OpenCL and Liquid Metal (Lime)

High-level programming models focusing on improving portability 7/63 Approach RCMW composed of three layers Translation Layer Converts platform-specific resource interfaces to a standardized RCMW interface Presentation Layer

Uses the RCMW interface to provide user specified resource requirements Application Layer Final interfaces allow user to develop application without platform dependencies 8/63 Translation Layer (HW) Converts vendor-specified physical interfaces to an RCMW-standardized interface format

Including interfaces for inter-FPGA communication, memories, and host communication RCMW-standardized interface can then be integrated further in the Presentation layer Exposes FPGA block RAM on the device Allows for the user to implement lower-latency OCM 9/63

Presentation Layer (HW) Converts standardized physical resources into resources usable by the application Consulting the RCMW IP database Contains components for arbitration, interface conversion and controllers, and multiplexing Variable number of interfaces can be provided in FIFO or burst mode Configured via XML framework

Interfaces, pin assignments, and timing constraints 10/63 Presentation Layer (HW) Resource Arbitration Resource Arbitration allows for multiple interfaces to map to a single physical interface Bandwidth to support multiple interfaces Coordinated via arbitration controller

Ready-to-send (RTS) and clear-to-send (CTS) signals RTS signal Asserted when a configurable number of bytes remains in the buffer, indicating the controller is ready to access memory CTS signal Asserted when the interface takes control of the physical memory bus De-asserted when the interface gives up control of the physical memory bus 11/63

Application Layer (HW) Provides application-specific hardware interfaces required by the user Interface provided in the form of a top-level entity No knowledge required of underlying hardware 12/63 Software Abstraction Implementation

13/63 Software Abstraction Provides object- oriented API based on C++11 C++11 used for improved threading and memory management Standardized register and memory

interfaces 14/63 Translation Layer (SW) Standardized interface exposed through Board class Each platform has subclass in board to implement Blocking reads/writes Non-blocking reads/writes Board enumeration Bitfile initialization Memory and FPGA objects inside board represent

physical components on platform Implemented using vendor-specific API or RCMWspecific driver interface 15/63 Presentation Layer (SW) Generated as subclass of RCMW application class Application class encapsulates instances of resource interface objects requested in the XML specification At runtime Loads bitfile

Initializes memory interfaces (calls bind) Runs user code (calls execute) Resources automatically released at end of execution 16/63 Application Layer (SW) Implemented by application class Only need to build app in execute stub Improves productivity Thread-safe timing library

17/63 RC Middleware Toolset Handles generating presentation layer Maps application resources onto platform resources Three-step generation Parsing XML description Mapping application to platform resources Generates HDL/C++ for interfaces Structural HDL generated for hardware instances Application class software created in C++

Makefile also generated to ease compilation 18/63 RC Middleware Tool Flow 19/63 Mapping Most complex step in presentation layer generation Determines locations of memory and FIFO resources Mappings vary greatly between target platforms Iterates through all application to physical

mappings Evaluates with cost function Lowest cost mapping gets used Cost function based on number of IP instances and metadata information Metadata about interfaces used to help evaluate cost Maximum operating frequency Device resource utilization reports 20/63 Experimental Results 21/63

Experimental Setup Three different platforms were used for testing GiDEL PROCStar III Altera Stratix III FPGA 4 GB DDR2 and 256 MB SDRAM per FPGA GiDEL PROCStar IV Altera Stratix IV FPGA 8 GB DDR2 and 512 MB SDRAM per FPGA

Pico Computing M501 Xilinx Virtex-6 512 MB DDR3 per FPGA 22/63 Experimental Setup Software used: Quartus II v11.1 for Altera bitfile generation Used GiDEL drivers for PROCStar board tests Xilinx ISE 14.1 for Xilinx bitfile generation Used with Pico boards

GCC with C++11 support using O3 optimizations Used for compiling the RCMWs software API 23/63 Performance Analysis Native and RCMW implementations compared Performance overhead was analyzed in two ways

Read and Write performance Measured by timing memory transfers from the host and FPGA Tested with a variety of data sizes Area overhead Measured using post-fit component device utilization summary generated by Quartus and ISE 24/63 Performance Analysis Greatest overhead occurred between the host

and external memory PROCStar III was the worst at 80% overhead Overhead was caused by RCMWs additional features Thread-safety mainly to blame M501 has thread-safety built in Performs better than both other boards Transfer size had large effect on overhead Overhead approaches zero for large transfer sizes

Overhead increased transfer time by 25/63 26/63 Area Analysis Area split up into three categories RCMW Logic overhead of middleware components Application

Area usage dedicated to implementing benchmark Vendor IP Consists of vendor supplied IP such as memory controllers, FPGA to host interface (PCIe), PLLs, etc RCMW typically took less than 1% of total fabric area This can vary depending on the number of interfaces

27/63 28/63 Productivity Analysis Split into three metrics Software lines of code (SLoC) Hardware lines of code (HLoC) Total development time Each benchmark was ported to the hardware platform from existing OpenCores IP Same developer worked on all the benchmarks

This ensured number of lines of code stayed consistent 29/63 Productivity Analysis RCMW required much less development than native GiDEL (Altera) 65% less SLoC 41% less HLoC 53% less development time

Pico (Xilinx) 66% less SLoC 59% less HLoC 69% less development time 30/63 Portability Analysis RCMW makes it possible to easily port projects between diverse hardware platforms RCMW toolset executed only once per platform Architectural differences did affect

performance Benchmarks requiring more memory interfaces like image segmentation ran better on GiDEL hardware Pico hardware supported a newer PCIe standard which increased the speed of the 31/63 host-FPGA connection Overall Performance 32/63

Conclusions Drastically decreased the amount of time/coding required for the development Increased the portability of FPGA apps between hardware platforms Allows developer to code from an application centric viewpoint and not worry about low level hardware 33/63 Future Work Larger case study to fully evaluate RCMW

productivity Variety of developers and applications needed to fully flesh out the effectiveness of the middleware Vendor specific IP cores hurt portability Work is needed to be able to enable interoperability of vendor cores like memory and interface controllers 34/63

Programming Transparency and Portable Hardware Interfacing Towards General-Purpose Reconfigurable Computing 35/63 Introduction Two main types of computation Temporal computation Computation running on general processors Most common Spatial computation

Computation in specifically-designed hardware for a particular application Application specific 36/63 FPGA Pros and Cons Pros FPGAs provide flexibility for spatial tasks without developing ASICs ASICs even more expensive, not reprogrammable

Allow for design growth of unit through re-programmability Cons Higher unit cost for FPGAs compared to processors Reduces large-scale production abilities Slower clock speed than processors and ASICs

37/63 Reconfigurable System-on-Chip Lack of unified programming methodology Increases difficulty of software development No standardized interfaces for hardware accelerators Makes portability difficult Must be easier to program and more portable Make RC systems better for general-purpose computing

38/63 Microprocessors vs RC Devices Microprocessors Easily programmed and run on abstraction layers OS, libraries, virtual machines Hide platform specific details RC devices Software and hardware need to be written and interfaced Exposed platform-dependent communication details to programmer Difficult to manage

Less portable 39/63 Goal New programming paradigm for RC devices Decoupled from underlying platform App-level programmers dont have information about hardware Hardware designers not exposed to interfacing details Dont know where data to be processed is located

Underlying architecture provides abstraction layer to fit between hardware and software design Supports programming model Abstraction layer provides transparency and uses 40/63 standard interfacing between software and Transparent Programming Model Application Programmers Code high-level concepts without knowledge of

underlying platform Could be sequential or parallel code Authors considered parallel multithreaded model Shared memory paradigm 41/63

Multithreaded Programming Model Co-routine execution First approach to multithreading without system-level support Common multithreading supported by abstraction layer Ignores existence of hardware threads Extended multithreading

supports seamless integration of hardware threads Programming transparent Interfacing portable 42/63 Extended Abstraction Multithreaded apps achieved through coroutine execution Abstraction layer of libraries/OS support currently used for thread management Doesnt cover possibility for hardware threads

Non-standardized communication and interfacing Bad for hardware accelerators Solution Extend thread abstraction layer Provide support for standard integration of hardware threads Threads communicate over standardized interfaces Normal abstraction layer still in place 43/63 Designing Portable Software Architectures

44/63 Software Threads Underlying Goal: Portability General Guidelines Software thread should interface with virtualization layer and not hardware accelerators directly 45/63 Hardware Threads

Underlying Goal: Portability General Guidelines Hardware thread should interface with virtualization layer and not main memory directly Interconnect accessible via communication assistants 46/63 Architectural Effects

Portable code that abstracts the underlying hardware from the application designer Paper explicitly does not address resource management, just portability 47/63 Software Hardware Interaction Software initiates execution and passes parameters through virtualization layer to hardware accelerator Hardware Accelerator accesses memory and

synchronizes with other system components through communication assistant Address translations and memory copies go through virtualization layer Acceleration core passes result back, control is returned to the software thread 48/63 Software Hardware Interaction 49/63 Virtualization Layer - Outsides Software Threads

Abstracted via thread libraries and system software Designed by application developers to accomplish task Hardware Threads Abstracted via Communication Assistants Perform address translation and network interfacing Designed to accelerate software tasks 50/63

Virtualization Layer - Insides Inner abstraction to coordinate thread libraries with communication assistants Perform memory translations between software threads, hardware accelerators and local/central memory Perform additional processing, prefetching, or other advanced data management techniques 51/63

Advanced Techniques 52/63 Dynamic Optimizations Multiple layers of abstractions decreases efficiency Virtualization layer can be used for optimization Layer could detect memory access patterns Use this information to perform prefetching Hides communication latency

Can be used for detecting sequential data accesses E.g. Supplying data in advance for a Vector Addition 53/63 Automated Synthesis High level language concepts hard to map to hardware Pointers complicate hardware synthesis

Virtualization layer allows generation of memory addresses as they are Recursion handled by hardware thread calling itself Virtualization layer decides dynamically what to do If accelerator supports recursion then it runs as is If not then the layer will call a software equivalent of the hardware thread 54/63

Flexible Software Migration Allows runtime software to hardware migration Can add abstraction layers such as JVM Conserves compile-once-run-anywhere principle 55/63 Real Implementation

56/63 Programming Virtualization layer simplified using sequential execution model Eliminates memory consistency problems Layer implemented as Virtual Memory Window (VMW) Main function initializes data and passes virtual pointers to hardware accelerator Utilizes standardized OS services to call accelerator Switches back to software after hardware execution Obscures all communication details 57/63

Architecture Software runs on ARM processor Accesses memory through AMBA bus Hardware accelerator core instantiated into FPGA and accessed via Window Management Unit (WMA) WMU Acts as communication assistant for hardware core Translates virtual addresses to physical addresses

58/63 Results Ran multimedia benchmark ADPCM Decode Measured execution time Pure software Typical coprocessor (Directly programmed from user app) VMW-based version of coprocessor Significant improvement with the VMW version

Typical coprocessor achieved 20x speedup VMW-based version w/o prefetching 15x speedup w/ prefetching 23x speedup 59/63 Results Manage Time Time required manage WMU Copy Time Time required to copy pages to/from main memory Sleep Time Time while VMW manager sleeps waiting for

WMU 60/63 Conclusion Authors address problems that plague every RC system Lack of standardization for programming Lack of standardization for hardware designing Brings RC closer to general purpose computing needs Model suppresses difference between software and hardware from the viewpoint of the programmer Virtualization layer abstracts platform details

Despite overhead virtualization layer can be a big benefit Overhead actually can be leveraged to optimize on the fly Presented case study of a real reconfigurable system 61/63 Shortfalls Middleware Case study was limited to one developer Only mentions the problems with Vendor IP even though this is a huge problem for portability Portability

Only tested on one kernel so ADPCM Decode might be an outlier Paper spent a lot of time explaining basic programming concepts 62/63 Questions? 63/63

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