EE 4271 VLSI Design, Fall 2013 Sequential Circuits

EE 4271 VLSI Design, Fall 2013 Sequential Circuits

EE 4271 VLSI Design, Fall 2013 Sequential Circuits Combinational Logic Combinational Logic: Output depends only on current input Has no memory 2020.02.06 Sequential Circuits PJF - 2 Sequential Logic Sequential Logic: Output depends not only on current input but also on past input values, e.g., design a counter Need some type of memory to remember the past input values 2020.02.06 Sequential Circuits PJF - 3

Sequential Circuits Circuits that we have learned so far Information Storing Circuits Timed States 2020.02.06 Sequential Circuits PJF - 4 Sequential Logic: Concept Sequential Logic circuits remember past inputs and past circuit state. Outputs from the system are fed back as new inputs With gate delay and wire delay The storage elements are circuits that are capable of storing binary information: memory. 2020.02.06

Sequential Circuits PJF - 5 Synchronous vs. Asynchronous There are two types of sequential circuits: Synchronous sequential circuit: circuit output changes only at some discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Asynchronous sequential circuit: circuit output can change at any time (clockless). 2020.02.06 Sequential Circuits PJF - 6 Synchronous Sequential Circuits: Flip flops as state memory The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram.

2020.02.06 Sequential Circuits PJF - 7 Clock Period FF Combinational Circuit FF FF Smallest clock period = largest combinational circuit delay between any two directly connected FF, subjected to impact of FF setup time. 2020.02.06 Sequential Circuits

PJF - 8 SR Latch (NAND version) 0 S 1 Q Q R X 0 0 1 1 2020.02.06 1 0 S 0 0

1 1 R 0 1 0 1 Q Q 1 0 Set Y NAND 0 1 1 1 0 1 1 0 Sequential Circuits PJF - 9 SR Latch (NAND version)

1 S 1 R X 0 0 1 1 2020.02.06 Q 1 Q 0 S 0 0 1 1

R Q Q 0 1 0 Set 1 0 1 0 Hold 1 Y NAND 0 1 1 1 0 1 1 0 Sequential Circuits PJF - 10 SR Latch (NAND version) 1 S 0

R X 0 0 1 1 2020.02.06 Q 0 Q 1 S 0 0 1 1 R Q Q 0 1 0 Set 1

0 1 Reset 0 1 0 Hold 1 Y NAND 0 1 1 1 0 1 1 0 Sequential Circuits PJF - 11 SR Latch (NAND version) 1 S 1 R X

0 0 1 1 2020.02.06 Q 0 Q 1 S 0 0 1 1 R Q Q 0 1 0 Set 1 0 1 Reset 0 1

1 0 Hold 0 1 Hold Y NAND 0 1 1 1 0 1 1 0 Sequential Circuits PJF - 12 SR Latch (NAND version) 0 S 0 R X 0 0

1 1 2020.02.06 Q 1 Q 1 S 0 0 1 1 R Q Q 0 1 1 Disallowed 1 0 Set 1 0 1 Reset 0 1 0 Hold 1 0 1 Hold

Y NAND 0 1 1 1 0 1 1 0 Sequential Circuits PJF - 13 SR Latch with Clock signal Latch is sensitive to input changes ONLY when C=1 2020.02.06 Sequential Circuits PJF - 14 D Latch One way to eliminate the undesirable indeterminate

state in the RS flip flop is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch: 2020.02.06 Sequential Circuits PJF - 15 D Latch with Transmission Gates 1 2 C=1 TG1 closes and TG2 opens Q=D and Q=D C=0 TG1 opens and TG2 closes Hold Q and 2020.02.06 Sequential Circuits PJF - 16 Q Flip-Flops Latches are transparent (= any change on

the inputs is seen at the outputs immediately when C=1). This causes synchronization problems. Solution: use latches to create flip-flops that can respond (update) only on specific times (instead of any time). Types: RS flip-flop and D flip-flop 2020.02.06 Sequential Circuits PJF - 17 Master-Slave FF configuration using SR latches 2020.02.06 Sequential Circuits PJF - 18 Master-Slave FF configuration using SR latches (cont.) S 0 0 0 1

1 0 1 1 X X R CLK Q Q 1 1 1 1 0 2020.02.06 Q0 Q0 0 1 1 0 1 1 Q0 Q0 When C=1, master is enabled Store and Reset stores new data, slave stores

Set old Disallowed data. Store When C=0, masters state passes to enabled slave, master not sensitive to new data (disabled). Sequential Circuits PJF - 19 D Flip-Flop 2020.02.06 Sequential Circuits PJF - 20 Characteristic Tables Defines the logical properties of a flip-flop (such as a truth table does for a logic gate). Q(t) present state at time t Q(t+1) next state at time t+1

2020.02.06 Sequential Circuits PJF - 21 Characteristic Tables (cont.) SR Flip-Flop 2020.02.06 S R Q(t+1) Operation 0 0 Q(t) No change/Hold

0 1 0 Reset 1 0 1 Set 1 1 ? Undefined/Invalid Sequential Circuits

PJF - 22 Characteristic Tables (cont.) D 0 1 D Flip-Flop Q(t+1) Operation 0 Set 1 Reset Characteristic Equation: Q(t+1) = D(t) 2020.02.06 Sequential Circuits PJF - 23 D Flip-Flop Timing Parameters 2020.02.06

Setup time Sequential Circuits PJF - 24 Sequential Circuit Analysis Analysis: Consists of obtaining a suitable description that demonstrates the time sequence of inputs, outputs, and states. Logic diagram: Boolean gates, flip-flops (of any kind), and appropriate interconnections. The logic diagram is derived from any of the following: Boolean Equations (FF-Inputs, Outputs) State Table State Diagram 2020.02.06 Sequential Circuits PJF - 25 Example

Input: x(t) Output: y(t) State: (A(t), B(t)) What is the Output x Q A C Q A Q B D Function?

D What is the Next State Function? CP C Q y 2020.02.06 Sequential Circuits PJF - 26 Example (continued) Boolean equations the functions: for x A(t+1) = A(t)x(t) B(t)x(t) B(t+1) = A(t)x(t)

D Q + C Q A A Next State y(t) = x(t)(B(t) + A(t)) D CP Q B C Q' y Output

2020.02.06 Sequential Circuits PJF - 27 State Table Characteristics State table a multiple variable table with the following four sections: Present State the values of the state variables for each allowed state. Input the input combinations allowed. Next-state the value of the state at time (t+1) based on the present state and the input. Output the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present State and the outputs are Output, Next State 2020.02.06 Sequential Circuits PJF - 28

Example: State Table The state table can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t); y(t) =x (t)(B(t) + A(t)) Present State Input A(t) 0 0 0 0 1 1 1 1 2020.02.06 B(t) 0 0 1 1 0 0

1 1 x(t) 0 1 0 1 0 1 0 1 Sequential Circuits Next State Output A(t+1) B(t+1) 0 0 0 1 0 0 1 1 0 0

1 0 0 0 1 0 y(t) 0 0 1 0 1 0 1 0 PJF - 29 State Diagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input values which causes the state transition, and

A label: On each circle with the output value produced, or On each directed arc with the output value produced. 2020.02.06 Sequential Circuits PJF - 30 Example: State Diagram x=0/y=0 x=0/y=1 x=1/y=0 Diagram gets confusing for AB 00 x=0/y=11 0 large circuits For small circuits, x=1/y=0 usually easier to x=1/y=0 understand than x=0/y=1

the state table 01 2020.02.06 Sequential Circuits 11 x=1/y=0 PJF - 31 Summary Sequential circuit timing analysis Flip-Flop Transmission gate based flip-flop design Setup time 2020.02.06 Sequential Circuits PJF - 32

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