NoC presentation - Technion

NoC presentation - Technion

ClubNet - November 2003 EE Department, Technion, Israel Network on Chip (NoC) Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny 1 Evgeny Bolotin ClubNet Nov 2003 Outline Motivation SoC Communication Current Solutions NoC Concept QNoC Arch. & Design Process QNoC Example NoC Cost Summary 2 Evgeny Bolotin ClubNet Nov 2003 Growing Chip Density 1998 Asic - 0.35 m

2003 SoC - 0.1 m Memory, I/O P Design complexity - high IP reuse Efficient high performance interconnect Scalability of communication architecture 3 Evgeny Bolotin ClubNet Nov 2003 The Growing Gap: Computation vs. Communication Taken From ITRS, 2001 4 Evgeny Bolotin ClubNet Nov 2003 The Gap: Something to think about Taken from W.J. Dally presentation: Computer architecture is all about interconnect (it is now and it will be more so in 2010) HPCA Panel February 4, 2002 5

Evgeny Bolotin ClubNet Nov 2003 SoC Interconnect Interconnect Dominates Delay and Power in VDSM Doesnt Scale with Technology: interconnect power + delay more dominant as the technology improves Globally Asynchronous Locally Synchronous (GALS ) Systems distributed systems on single silicon substrate 6 Evgeny Bolotin ClubNet Nov 2003 Bus Inheritance P P From Board level into Chip level 7 Evgeny Bolotin ClubNet Nov 2003 Typical Solution-Bus Shared Bus B

Segmented Bus 8 Evgeny Bolotin ClubNet Nov 2003 B Typical Solution-Bus Multi-Level Segmented Bus B Segmented Bus Original bus features: One transaction at a time Central Arbiter Limited bandwidth Synchronous Low cost Is it still? 9 Evgeny Bolotin ClubNet Nov 2003

B B B New features: Versatile bus architectures Pipelining capability Burst transfer Split transactions Transaction preemption and resume Transaction reordering Well-known Industry Solutions AMBA (Advanced Microcontroller Bus Architecture) Ownership: ARM SiliconBackplane Network Ownership: Sonics Core-Connect

Ownership: IBM 10 Evgeny Bolotin ClubNet Nov 2003 Traditional SoC Nightmare Variety of dedicated interfaces Poor separation between computation and communication. Design Complexity Unpredictable performance 11 Evgeny Bolotin ClubNet Nov 2003 Solution Network on Chip Networks are preferred over buses: 12 Higher bandwidth Concurrency, effective spatial reuse of resources Higher levels of abstraction

Modularity - Design Productivity Improvement Scalability Evgeny Bolotin ClubNet Nov 2003 Solution Network on Chip Requirements: Different QoS must be supported Bandwidth Latency Distributed deadlock free routing Distributed congestion/flow control Low VLSI Cost 13 Evgeny Bolotin ClubNet Nov 2003 NoC vs. Off-Chip Networks What is Different? M o d u le M o d u le M o d u le M o d u le M o d u le

M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le Routers on Planar Grid Topology Short PTP Links between routers Unique VLSI Cost Sensitivity: Area-Routers and Links Power 14 Evgeny Bolotin ClubNet Nov 2003 M o d u le NoC vs. Off-Chip Networks No legacy protocols to be compliant with No software simple and hardware efficient protocols

Different operating env. (no dynamic changes and failures) Custom Network Design You design what you need! Example1: Replace modules M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le

M o d u le Replace M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le 15 Evgeny Bolotin ClubNet Nov 2003 M o d u le M o d u le M o d u le M o d u le NoC vs. Off-Chip Networks Example2: Adapt Links M o d u le

M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le Adapt Links M o d u le M o d u le

M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le M o d u le Example3: Trim Unnecessary (ports, buffers, routers, links) 16 Evgeny Bolotin ClubNet Nov 2003 QNoC: QoS NoC Define Service Levels (SLs): Signaling Real-Time Read/Write (RD/WR) Block-Transfer Different QoS for each SL

17 Evgeny Bolotin ClubNet Nov 2003 QNoC Architecture Mesh Topology Fixed shortest path routing (X-Y) Simple Router (no tables, simple logic) Power efficient communication No deadlock scenario 18 Evgeny Bolotin ClubNet Nov 2003 QNoC Architecture Wormhole Routing For reduced buffering Wormhole Packet: d d r e sinfo) s Flit A(routing C o mFlit m and Flit Flit P a y lo a d

Flit Flit 19 Evgeny Bolotin ClubNet Nov 2003 S D QNoC Wormhole Router O u tp u t p o rts In p u t p o rts M o d u le S IG N A L M o d u le or a n o th e r ro u te r B u ffe rs S IG N A L R o u te r RT RT

R D /W R BLO CK BLO CK C o n tro l R o u tin g C R E D IT S IG N A L RT C R E D IT 20 Evgeny Bolotin ClubNet Nov 2003 CROSS-BAR R D /W R S c h e d u le r C R E D IT

S IG N A L RT R D /W R R D /W R BLO CK BLO CK C o n tro l R o u tin g S c h e d u le r C R E D IT QNoC Design Process Take full network and customize using a-priori known parameters M o d u le s w ith Id e a l N e tw o rk C h a r a c t e r iz e T r a ffic P la c e

m o d u le s Q N oC A r c h ite c tu r e M a p T r a f fic to G r id O p tim iz e E s tim a te c o s t 21 Evgeny Bolotin ClubNet Nov 2003 QNoC Design Process - Optimization Trim Unnecessary Resources Adjust each link capacity according to its load Equal link utilization across the chip Example: (Uniform mesh) 22 Evgeny Bolotin ClubNet Nov 2003 QNoC Design Process - Cost est. QNoC Cost : Total wire-length and FF-count Wire cost ~ wire-length

Cost wire area A0 W i l i i{QNoC links} where: A0 -wire pitch , W i - width of link i (number of wires), and l i - length of link i Dynamic Power ~ wire-length and U Costwire power ( Pd ) PU 0 f iW i l i i{QNoC links} where: P0 -constant coefficient, U -utilization of the links, f i -frequency of the link i. Logic Cost ~ FF-count Cost logic-area i{Routers}

23 Evgeny Bolotin ClubNet Nov 2003 # FF i 2 where: # FF # Port # SL FlitSize 2 BufSize log 2 BufSize # Port Design Example 24 Evgeny Bolotin ClubNet Nov 2003 Design Example Representative Design Example, each module contains 4 traffic sources: Traffic Source Traffic interpretation Average Packet

Length [flits] Average Inter-arrival time [ns] Total Load per Module ETE requirements For 99.9% of packets Signaling Every 100 cycles each module sends interrupt to a random target 2 100 320 Mbps 20 ns (several cycles) Real-Time

Periodic connection from each module: 320 voice channels of 64 Kb/s 40 2 000 320 Mbps 125 s (Voice-8 KHz frame) RD/WR Random target RD/WR transaction every ~25 cycles. 4 25 2.56 Gbps ~150 ns (tens of cycles)

Block-Transfer Random target BlockTransfer transaction every ~12 500 cycles . 2.56 Gbps 50 s (Several tx. delays on typ. bus) 25 Evgeny Bolotin ClubNet Nov 2003 2 000 12 500 Uniform Scenario - Observations Calculated Link Load Relations: 26 Evgeny Bolotin ClubNet Nov 2003 Uniform Scenario - Observations Various Link BW allocations: Packet ETE delay of packets [ns or cycles]

27 Allocated Link BW [Gbps] Average Link Utilization [%] Signaling (99.9%) Real-Time (99.9%) RD/WR (99%) BlockTransfer (99%) 2560Gbps 10.3 6

80 20 4 000 850Gbps 30.4 20 250 80 50 000 512Gbps 44 35 450 1 000 300 000

Evgeny Bolotin ClubNet Nov 2003 Desired QoS Uniform Scenario - Observations Fixed Network Configuration -Uniform Traffic Network behavior under different traffic loads? BLOCK ETE Delay Real-Time RD/WR 28 Traffic Load Evgeny Bolotin ClubNet Nov 2003 Signaling QNoC vs. Alternative Solutions (4x4 mesh, uniform traffic) Uniform scenario (Same QoS): Wire-Length(Area) and Power Arch. Frequency

Utilization Av. Link Width 100.0 Wire Length 45.0 QNoC 1GHz 30% Power 28 Bus PTP 50 MHz 100MHz 50%

80% 3 700 6 Cost 10.0 3.8 2.9 1.0 1.0 1.0 0.8 0.1 BUS NoC BUS QNoC 29 Evgeny Bolotin ClubNet Nov 2003

PTP PTP NoC Cost Scalability vs. Alternatives Compare the cost of: NoC d d n d Non-Segmented Bus (NS-Bus) n n d n Segmented Bus (S-Bus) d

n d n Point-To-Point (PTP) 30 Evgeny Bolotin ClubNet Nov 2003 NoC Cost Scalability vs. Alternatives 31 Total Area 1 O 2 n 1 O n

O n n O n n NoC O n O n2 n Operating Frequency O n2 n Evgeny Bolotin ClubNet Nov 2003 Power Dissipation

O n3 n PTP S-Bus NS-Bus Arch O n O 1 1 O n O n n Summary

32 Why NoC? What is Different in NoC QNoC NoC is Best Evgeny Bolotin ClubNet Nov 2003

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