Impact of Interconnect Interconnection Fundamental limitation of Digital
Impact of Interconnect Interconnection Fundamental limitation of Digital Technology at all scales Classes of parasitics: Capacitive Resistive Inductive (Impact usually package/board level) Digital Integrated Circuits2nd Inverter Interconnect Impact on Chip Digital Integrated Circuits2nd
Inverter Nature of Interconnect No of nets (Log Scale) Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II Global Interconnect SGlobal = SDie
aF/m 52 aF/m Inverter INTERCONNECT Resistance Digital Integrated Circuits2nd Inverter Wire Resistance R= L
HW Sheet Resistance Ro L H W Digital Integrated Circuits2nd R1 R2 Inverter Interconnect Resistance
Digital Integrated Circuits2nd Inverter Polycide Gate MOSFET Silicide PolySilicon SiO2 n+ n+ p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly
Digital Integrated Circuits2nd Inverter Sheet Resistance Digital Integrated Circuits2nd Inverter Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric Digital Integrated Circuits2nd Inverter
Interconnect Modeling Digital Integrated Circuits2nd Inverter The Lumped Model Vo ut cwi re Driver R d r iv e r Vout V in
C lu m p e d Digital Integrated Circuits2nd Inverter The Lumped RC-Model The Elmore Delay Digital Integrated Circuits2nd Inverter The Ellmore Delay RC Chain Digital Integrated Circuits2nd
Inverter Wire Model Assume: Wire modeled by N equal-length segments For large values of N: Digital Integrated Circuits2nd Inverter The Distributed RC-line Digital Integrated Circuits2nd Inverter Step-response of RC wire as a
function of time and space 2.5 x= L/10 2 voltage (V) x = L/4 1.5 x = L/2 1 x= L 0.5 0 0
0.5 Digital Integrated Circuits2nd 1 1.5 2 2.5 3 time (nsec) 3.5 4
4.5 5 Inverter RC-Models Digital Integrated Circuits2nd Inverter Driving an RC-line Rs (r w,cw,L)
V o ut V in Digital Integrated Circuits2nd Inverter Design Rules of Thumb rc delays should only be considered when tpRC >> tpgate of the driving gate Lcrit >> tpgate/0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line trise < RC
when not met, the change in the signal is slower than the propagation delay of the wire Digital Integrated Circuits2nd MJIrwin, PSU, 2000 Inverter Homework 4 1. 2. For the AMIS 0.5um technology, create an equivalent RC/Elmore SUE model using the Mosis parametric test results (amis05.txt from web site). This model should include the effective gate capacitance, source and drain parasitic junction capacitances and equivalent resistance for NMOS and PMOS,
L=0.5um as a function of W in um. Use this model to estimate the sizes of the transistors in the ring oscillator test for the standard and wide case from the given performance data. (Do this carefully, this is a useful model!!) Rabaey Chap. 4 on-line problems: 1, 4, 7, 12 Digital Integrated Circuits2nd Inverter
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