MIPSfpga Using a Commercial MIPS SoftCore in Computer Architecture Education Sarah L. Harris, University of Nevada, Las Vegas WCAE 2017 MIPSfpga <1> Overview Introduction MIPSfpga Overview Labs Example Courses and Applications Conclusion
WCAE 2017 MIPSfpga <2> Introduction What is MIPSfpga? MIPSfpga is an unobfuscated soft-core commercial MIPS processor available from Imagination Technologies for academic use. MIPSfpga supporting material is provided in three packages: MIPSfpga Getting Started Guide MIPSfpga Labs MIPSfpga SoC WCAE 2017 MIPSfpga <3>
MIPSfpga Materials MIPSfpga Getting Started Guide Overall MIPSfpga system, setup, and tools Verilog files for the MIPSfpga core and system MIPSfpga Labs 25 hands-on labs for experimenting with, analyzing, and modifying the MIPSfpga system MIPSfpga SoC MIPSfpga as the core of a system-on-chip that runs Linux WCAE 2017 MIPSfpga <4> MIPSfpga System MIPSfpga Core
Soft-core available in Verilog System modules available in Verilog and VHDL WCAE 2017 MIPSfpga <5> MIPSfpga: microAptiv Core Commercial microAptiv core 5-stage pipeline Set-associative I & D caches MMU (memory management unit) with TLB Performance counters No DSP, Coprocessor 2, or shadow registers Interfaces:
AHB-Lite bus EJTAG programmer/debugger CorExtend for user-defined instructions WCAE 2017 MIPSfpga <6> How to Run Programs on MIPSfpga? In Simulation: ModelSim Vivado built-in simulator In Hardware: Load program into memory: at synthesis using EJTAG interface (using Bus Blaster Probe) using UART interface (i.e., using Nexys4 DDRs existing programming cable or USB-UART FTDI board) WCAE 2017
MIPSfpga <7> FPGA boards Support for Nexys4 DDR and DE2-115 boards Instructions on how to port it to other FPGA boards (end of Lab 1) Nexys4 DDR WCAE 2017 DE2-115 MIPSfpga <8> System setup: Nexys4 DDR + BusBlaster To USB port Nexys4 DDR Board
To USB port Bus Blaster Probe WCAE 2017 MIPSfpga <9> Overview Introduction MIPSfpga Overview Labs Example Courses and Applications
Conclusion WCAE 2017 MIPSfpga <10> MIPSfpga Labs Hands-on learning in areas including: System-on-chip (SoC) design Assembly language and C programming Instruction set architectures (ISAs)
Design with hardware description languages (HDLs) Computer architecture Memory systems Memory-mapped I/O and interfacing with peripherals Interrupts Performance Counters WCAE 2017 MIPSfpga <11> MIPSfpga Labs Organized into four sections: Intro (Labs 1-4) I/O (Labs 5-13) Core (Labs 14-19)
20 Basic caching 21 Cache structure 22 Cache controller: Hit & miss management 23 Cache controller: Content management 24 Cache controller: Store and fill buffers
25 Scratchpad RAM MIPSfpga <14> Overview Introduction MIPSfpga Overview Labs Example Courses and Applications Conclusion WCAE 2017
MIPSfpga <15> Example Courses and Applications Course 1: 4th year Integrated Systems Architecture Course Course 2: 4th year/Masters level Processor and I/O Systems Lab Hackathon MIPSfpga is best used after learning the basics of Digital Design, HDLs, and Computer Architecture. WCAE 2017 MIPSfpga <16> Ex. 1: Systems Architecture Course At UCM (Universidad Complutense de Madrid) 2017 Student background Digital & HDL design (VHDL) Computer Organization (MIPS ISA, single/multicycle processors, I/O systems)
Programming (C++) WCAE 2017 MIPSfpga <17> Course Contents Module 1: Review: MIPS ISA, single/multi-cycle processors, I/O systems Module 2: Pipelined processors Module 3: Caches Module 4: SoC and embedded system design WCAE 2017
MIPSfpga <18> Course Materials Textbook: Digital Design and Computer Architecture, 2nd Edition (Harris & Harris, Elsevier 2012) Slides: Extended versions of the slides provided with the book and with MIPSfpga Labs Labs: MIPSfpga materials (MIPSfpga Labs and MIPSfpga SoC) Exercises: Worksheets adapted from textbook and labs WCAE 2017 MIPSfpga <19> Course Schedule
Lectures: 24 1.5-hour lessons, 2 per week Lab sessions 12 2-hour sessions, 1 per week Module 1: MIPS ISA & Hardware (5 weeks) Install MIPSfpga tools and build MIPSfpga in Vivado (MIPS GSG & Lab 1) Review MIPS ISA: assembly & C programming (Labs 2-4) Review: I/O Systems (Lab 5: Add 7-segment displays) Module 2: Pipelined Processor (3 weeks) Labs 13-18 (ADD, AND, LW, BEQ instruction flow, Hazard Unit) Module 3: Cache Hierarchy (3 weeks) Labs 22A and 22B (Cache hits, Cache misses) Module 4: SoC and Embedded System Design (1 week) MIPSfpga SoC Starter Tutorial WCAE 2017 MIPSfpga <20> Ex. 2: Processor & I/O Systems Lab
At TUD (Technical University of Darmstadt, Germany) in 2016 Student background Digital & HDL design (VHDL) Computer Organization (MIPS ISA, single/multicycle processors, I/O systems) Programming WCAE 2017 MIPSfpga <21> Course Materials Textbook: Digital Design and Computer Architecture, 2 nd Edition (Harris & Harris, Elsevier 2012) Slides: Extended versions of the slides provided with the book and MIPSfpga Labs Labs:
Ex. 3: Hackathon Seminars in Russia, Ukraine and Kazakhstan in 2015/2016 MIPSfpga integrated into courses / labs Culminated in Hackathon where students interfaced MIPSfpga to peripherals using SPI, I2C, etc. (see MIPSfpga I/O Labs) http://store.digilentinc.com/pmod-expansion-modules/pmod-boards/ WCAE 2017 MIPSfpga <24> Overview
Introduction MIPSfpga Overview Labs Example Courses and Applications Conclusion WCAE 2017 MIPSfpga <25> MIPSfpga Comparisons Name Comparisons Nios, Nios II, Microblaze, Cortex M0 Design Start + Soft-core - Obfuscated
OpenSPARC, Leon + Soft-core + Open-source - Few teaching materials - ISA not commonly used in academia RISC-V, openRISC + Soft-core + Open-source - Not a commercial core - Few teaching materials MIPSfpga: + Unobfuscated soft-core + Commercial core (e.g., used in Microchips PIC32MZ) + Commonly taught ISA in academia + Robust teaching materials
WCAE 2017 MIPSfpga <26> Conclusions MIPSfpga bridges the gap between toy processors and industry-level processors. MIPSfpga is an excellent resource for courses in: Digital design, computer architecture, embedded systems, Memory systems, VLSI design, SoC design MIPSfpga offers robust teaching materials best used in upper-division undergraduate or masters-level courses. WCAE 2017 MIPSfpga <27> MIPSfpga Materials & Support
MIPSfpga materials available on the Imagination University Program Website under Teaching Materials: http://community.imgtec.com/university/university-registration MIPSfpga Forum (technical support): http://community.imgtec.com/forums/cat/mips-insider/mipsfpga/ Other Forums MIPS Tech Support (general questions): http://community.imgtec.com/forums/cat/mips-insider/ Imagination University Programme (curriculum discussions, IUP questions, etc. no tech support): http://community.imgtec.com/forums/cat/university/ WCAE 2017 MIPSfpga <28> Acknowledgements
Robert Owen Sarah Harris Daniel Chaver-Martinez David Money Harris Yuri Panchul Bruce Ableidinger Enrique Sedano Zubair Kakakhel
Kent Brinkley Chuck Swartley Akhilesh Sandeep Thakur Christian White WCAE 2017 Sean Raby Rick Leatherman
Matthew Fortune Munir Hasan Sachin Sundar Michael Alexander Sam Bobrowicz Cathal McCabe Roy Kravitz Alexey Pereverzev Nicholas Beser
Larissa Swanland Clint Cole Students and faculty at UCL Ian Oliver Steve Kromer Parimal Patel Jason Wong Zhe Yang Professor Dai Zhongzheng (Jason) Wang Bin He Dennis Pinto MIPSfpga <29> Thank you! Any questions? WCAE 2017
2 I E Instruction Execution 3 4 M A Memory Align 5 W
Writeback Fetch Instruction Fetch operands from RF & perform ALU operation Access Memory Align data to word boundary Write result to RF WCAE 2017 MIPSfpga <33> MIPSfpga Memory Map 32-bit virtual memory space (0x00000000 0xFFFFFFFF), broken up into different segments On reset, processor begins in kernel mode and jumps to the
reset vector at address 0xBFC00000 (mapped to physical address 0x1FC00000) WCAE 2017 MIPSfpga <34> MIPSfpga System: Physical Memory Boot Code: Code executed at startup (128 KB) User Code/Data (256 KB) WCAE 2017 MIPSfpga <35> MIPSfpga Interfaces: AHB-Lite
Signal Name HADDR[31:0] Description Address bus HRDATA[31:0] HWDATA[31:0] HWRITE HCLK Read data bus Write data bus Write enable Clock H: prefix for AHB-Lite Interface signals in Verilog files WCAE 2017 MIPSfpga <36>
0xbf800008 0xbf80000c 0x1f800008 0x1f80000c Write to 0xbf800000 writes to LEDs Read from 0xbf800008 reads value of switches // Read value of switches into $10 lui $5, 0xbf80 # $5 = 0xbf800000 lw $10, 8($5) # $10 = value of switches WCAE 2017 MIPSfpga <42> Exampe Labs
WCAE 2017 MIPSfpga <43> Example: Lab 4 (Part 1) Image Transformation: Skeleton code students complete in C 2 extra exercises students complete in MIPS assembly Test/run lab on MIPSfpga WCAE 2017 MIPSfpga <44> Example: Lab 13 (Part 2) MIPS Pipelined Processor from book
ADDI $t4,$0,1000 Loop1: BEQ $t3,$t4,Out LW $t5,0($t0) ADD $t1,$t1,$t5 ADDI $t0,$t0,4 ADDI $t3,$t3,1 B Loop1 Out: LUI $t3, 0x8000 ADDIU $t3, $t3, Addition SW $t1,0($t3) WCAE 2017 Analyze the data and
control hazards: Processor from the book MicroAptiv Determine CPI for the processor from the book Determine CPI for microAptiv and measure it Reorder the code and repeat the exercise MIPSfpga <47> Lab 14: Add Instruction WCAE 2017 MIPSfpga <48> Example: Lab 22-B: D$ Misses (Part 3) Goal: Analyze I$/D$ miss management
Theoretical explanation of D$ miss management D$ miss simulations Exercises: Analyze a D$ hit Determine the miss penalty Code optimization techniques Array enlargement and array merging Loop interchange Blocking WCAE 2017 MIPSfpga <49> Example: MIPSfpga-SoC Starter Tutorial Build a System On Chip based on microAptiv core and Xilinx IP blocks WCAE 2017 MIPSfpga <50>
MIPSfpga-SoC Starter Tutorial Run Linux and play with it 1. 2. 3. 4. 5. 6. 7. 8. Download the Bitstream Terminal Emulation putty Run the bootram code Load Linux to memory via EJTAG Booting Linux Writing and Compiling a Program Reading the onboard temperature sensor via sysfs Accessing general-purpose I/Os via sysfs
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