Computer Architecture and Engineering Lecture 6: The Design ...

Computer Architecture and Engineering Lecture 6: The Design ...

CS152 Computer Architecture and Engineering Lecture 6 VHDL, Multiply, Shift CS152 Lec6.1 Representation Languages Hardware Representation Languages: Block Diagrams: FUs, Registers, & Dataflows Register Transfer Diagrams: Choice of busses to connect FUs, Regs Flowcharts State Diagrams Two different ways to describe sequencing & microoperations Fifth Representation "Language": Hardware Description Languages E.G., ISP' VHDL Verilog hw modules described like programs with i/o ports, internal state, & parallel execution of assignment statements Descriptions in these languages can be used as input to simulation systems "software breadboard" synthesis systems generate hw from high level description "To Design is to Represent" CS152 Lec6.2 Simulation Before Construction "Physical Breadboarding" discrete components/lower scale integration preceeds actual construction of prototype

verify initial design concept Simulation Before Construction high level constructs implies faster to construct play "what if" more easily limited performance accuracy, however CS152 Lec6.3 Levels of Description Architectural Simulation models programmer's view at a high level; written in your favorite programming language Functional/Behavioral more detailed model, like the block diagram view Register Transfer commitment to datapath FUs, registers, busses; register xfer operations are clock phase accurate Logic model is in terms of logic gates; higher level MSI functions described in terms of these Circuit Less Abstract More Accurate Slower Simulation

electrical behavior; accurate waveforms Schematic capture + logic simulation package like Powerview Special languages + simulation systems for describing the inherent parallel activity in hardware CS152 Lec6.4 VHDL (VHSIC Hardware Description Language) Goals: Support design, documentation, and simulation of hardware Digital system level to gate level Technology Insertion Concepts: Design entity Time-based execution model. Interface == External Characteristics Design Entity == Hardware Component Architecture (Body ) == Internal Behavior or Structure CS152 Lec6.5 Interface Externally Visible Characterisitcs Ports: channels of communication - (inputs, outputs, clocks, control) Generic Parameters: define class of components - (timing characterisitcs, size, fan-out) --- determined where instantiated or by default Internally Visible Characteristics Declarations: Assertions: constraints on all alternative bodies (i.e., implementations) Interface

Architecture view to other modules details of implementation CS152 Lec6.6 VHDL Example: nand gate ENTITY nand is PORT (a,b: IN VLBIT; y: OUT VLBIT) END nand ARCHITECTURE behavioral OF nand is BEGIN y <= a NAND b; END behavioral; Entity describes interface Architecture give behavior, i.e., function y is a signal, not a variable it changes when ever the inputs change drive a signal NAND process is in an infinite loop VLBit is 0, 1, X or Z CS152 Lec6.7 Modeling Delays ENTITY nand is PORT (a,b: IN VLBIT; y: OUT VLBIT) END nand ARCHITECTURE behavioral OF nand is BEGIN y <= a NAND b after 1 ns; END behavioral; Model temporal, as well as functional behavior, with delays in signal statements; Time is one difference from programming languages y changes 1 ns after a or b changes This fixed delay is inflexible hard to reflect changes in technology CS152 Lec6.8 Generic Parameters

ENTITY nand is GENERIC (delay: TIME := 1ns); PORT (a,b: IN VLBIT; y: OUT VLBIT) END nand ARCHITECTURE behavioral OF nand is BEGIN y <= a NAND b AFTER delay; END behavioral; Generic parameters provide default values may be overridden on each instance attach value to symbol as attribute Separate functional and temporal models How would you describe fix-delay + slope * load model? CS152 Lec6.9 Bit-vector data type ENTITY nand32 is PORT (a,b: IN VLBIT_1D ( 31 downto 0); y: OUT VLBIT_1D ( 31 downto 0) END nand32 ARCHITECTURE behavioral OF nand32 is BEGIN y <= a NAND b; END behavioral; VLBIT_1D ( 31 downto 0) is equivalent to powerview 32-bit bus Can convert it to a 32 bit integer CS152 Lec6.10 Arithmetic Operations ENTITY add32 is PORT (a,b: IN VLBIT_1D ( 31 downto 0); y: OUT VLBIT_1D ( 31 downto 0) END add32 ARCHITECTURE behavioral OF add32 is BEGIN y <= addum(a, b) ; END behavioral; addum (see VHDL ref. appendix C) adds two n-bit vectors to produce an

n+1 bit vector except when n = 32! CS152 Lec6.11 Control Constructs entity MUX32X2 is generic (output_delay : TIME := 4 ns); port(A,B: in vlbit_1d(31 downto 0); DOUT: out vlbit_1d(31 downto 0); SEL: in vlbit); end MUX32X2; Process fires whenever is sensitivity list changes Evaluates the body sequentially VHDL provide case statements as well architecture behavior of MUX32X2 is begin mux32x2_process: process(A, B, SEL) begin if (vlb2int(SEL) = 0) then DOUT <= A after output_delay; else DOUT <= B after output_delay; end if; end process; end behavior; CS152 Lec6.12

MIPS arithmetic instructions Instruction Example add subtract add immediate add unsigned subtract unsigned add imm. unsign. multiply multiply unsigned divide Meaning add $1,$2,$3 $1 = $2 + $3 sub $1,$2,$3 $1 = $2 $3 addi $1,$2,100 $1 = $2 + 100 addu $1,$2,$3 $1 = $2 + $3 subu $1,$2,$3 $1 = $2 $3 addiu $1,$2,100 $1 = $2 + 100 mult $2,$3 Hi, Lo = $2 x $3 multu$2,$3 Hi, Lo = $2 x $3 div $2,$3 Lo = $2 $3, divide unsigned divu $2,$3 Lo = $2 $3, Move from Hi Move from Lo

mfhi $1 mflo $1 $1 = Hi $1 = Lo Comments 3 operands; exception possible 3 operands; exception possible + constant; exception possible 3 operands; no exceptions 3 operands; no exceptions + constant; no exceptions 64-bit signed product 64-bit unsigned product Lo = quotient, Hi = remainder Hi = $2 mod $3 Unsigned quotient & remainder Hi = $2 mod $3 Used to get copy of Hi Used to get copy of Lo CS152 Lec6.13 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand Multiplier 1001 1000 0000 0000 1000 Product 01001000 1000 m bits x n bits = m+n bit product Binary makes it easy: 0 => place 0 ( 0 x multiplicand)

1 => place a copy ( 1 x multiplicand) 4 versions of multiply hardware & algorithm: successive refinement CS152 Lec6.14 Unsigned Combinational Multiplier 0 A3 A3 A3 A3 P7 P6 A2 A2 A1 P5 A2 A1 0 A2 A1 0 A1 0 A0 B0

A0 B1 A0 B2 A0 P4 B3 P3 P2 P1 P0 Stage i accumulates A * 2 i if Bi == 1 Q: How much hardware for 32 bit multiplier? Critical path? CS152 Lec6.15 Carry Save addition of 4 integers C 2 Add Columns first, then rows! I1 B2 A2 C1 B1 A1 C0 B0 A0 I2 I1

I1 I3 Carry Save Adder 3=>2 Can be used to reduce critical path of multiply S1 Example: 53 bit multiply (for floating point): At least 53 levels with nave technique Only 9 with Carry save addition! I2 I3 Carry Save Adder 3=>2 S0 S1 D2 I1 I2 I3 S1 S0 S1 S0

D0 I1 I2 I3 S1 0 I1 Carry Save Adder 3=>2 S0 I3 Carry Save Adder 3=>2 D1 Carry Save Adder 3=>2 I2 I2 I3 Carry Save Adder 3=>2 S0 S1 S0 0 I1

I2 I3 Carry Save Adder 3=>2 S1 S0 S4 S3 I1 I2 I3 Carry Save Adder 3=>2 S1 S0 S2 I1 I2 I3 Carry Save Adder 3=>2 S1 S0 S1 S0 CS152 Lec6.16 How does it

work? 0 0 0 A3 A3 A3 P7 P6 A2 P5 A2 A1 P4 0 A3 A2 A1 0 A2 A1 0 A1 0 A0 A0 B1 A0 B2 A0

P3 B0 B3 P2 P1 P0 at each stage shift A left ( x 2) use next bit of B to determine whether to add in shifted multiplicand accumulate 2n bit partial product at each stage CS152 Lec6.17 Unisigned shift-add multiplier (version 1) 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Shift Left Multiplicand 64 bits Multiplier 64-bit ALU Product Shift Right 32 bits Write 64 bits Multiplier = datapath + control Control CS152 Lec6.18

Multiply Algorithm Version 1 Multiplier0 = 1 Start Multiplier0 = 0 1. Test Multiplier0 1a. Add multiplicand to product & place the result in Product register Product Multiplier 0000 0000 0011 Multiplicand 0000 0010 2. Shift the Multiplicand register left 1 bit. 0000 0010 0001 0000 0100 0000 0110 0000 0000 1000 0000 0110 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions CS152 Done Lec6.19 Observations on Multiply Version 1 1 clock per cycle => 100 clocks per multiply

Ratio of multiply to add 5:1 to 100:1 1/2 bits in multiplicand always 0 => 64-bit adder is wasted 0s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed Instead of shifting multiplicand to left, shift product to right? CS152 Lec6.20 MULTIPLY HARDWARE Version 2 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 32 bits Multiplier 32-bit ALU Shift Right 32 bits Shift Right Product 64 bits Control Write CS152 Lec6.21 How to think of this? Remember original combinational multiplier: 0 A3 A3 A3 A3

P7 P6 A2 A2 A1 P5 A2 A1 0 A2 A1 0 A1 0 A0 B0 A0 B1 A0 B2 A0 P4 B3 P3 P2

P1 P0 CS152 Lec6.22 Simply warp to let product move right... 0 0 0 0 A3 A2 A1 A0 A3 A2 A1 A0 B0 B1 A3 A2 A1 A0 A3 A2 A1 A0

P7 P6 P5 B2 B3 P4 P3 P2 P1 P0 Multiplicand stays still and product moves right CS152 Lec6.23 Multiply Algorithm Version 2 Multiplier0 = 1 Start 1. Test Multiplier0 Multiplier0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Product Multiplier Multiplicand 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010

1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done CS152 Lec6.24 Start Still more wasted space! Multiplier0 = 1 1. Test Multiplier0

Multiplier0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Product Multiplier Multiplicand 1: 2: 3: 1: 2: 3: 1: 2: 3: 1: 2: 3: 0000 0000 0010 0000 0001 0000 0001 0000 0011 0000 0001 1000 0001 1000 0001 1000 0000 1100 0000 1100 0000 1100 0000 0110 0000 0110 0011 0011 0011 0001 0001 0001 0000 0000 0000 0000 0000 0000 0000

0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0000 0110 0000 0010 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done CS152 Lec6.25 Observations on Multiply Version 2 Product register wastes space that exactly matches size of multiplier => combine Multiplier register and Product register CS152 Lec6.26 MULTIPLY HARDWARE Version 3 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg)

Multiplicand 32 bits 32-bit ALU Shift Right Product (Multiplier) 64 bits Control Write CS152 Lec6.27 Multiply Algorithm Version 3 Multiplicand Product 0010 0000 0011 Product0 = 1 Start 1. Test Product0 Product0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions CS152 Done Lec6.28 Observations on Multiply Version

3 2 steps per bit because Multiplier & Product combined MIPS registers Hi and Lo are left and right half of Product Gives us MIPS instruction MultU How can you make it faster? What about signed multiplication? easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) apply definition of 2s complement - need to sign-extend partial products and subtract at the end Booths Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles - can handle multiple bits at a time CS152 Lec6.29 Motivation for Booths Algorithm Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 + 0010 + 0010 + 0000 00001100 shift (0 in multiplier) add (1 in multiplier) add (1 in multiplier) shift (0 in multiplier) ALU with add or subtract gets same result in more than one way: 6 = 2 + 8 0110

= 00010 + 01000 = 11110 + 01000 For example x . . 1) + 0010 0110 0000 shift (0 in multiplier) 0010 sub (first 1 in multpl.) 0000 shift (mid string of 1s) 0010 add (prior step had last 00001100 CS152 Lec6.30 Booths Algorithm end of run middle of run beginning of run 0 1 1 1 1 0 Current Bit Bit to the Right Explanation Example Op 1 0

Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift was faster than add) Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one 1 + 10000 01111 CS152 Lec6.31 Booths Example (2 x

7) Operation Multiplicand Product next? 0. initial value 0010 0000 0111 0 10 -> sub 1a. P = P - m 1110 + 1110 1110 0111 0 1b. 0010 1111 0011 1 11 -> nop, shift 2. 0010 1111 1001 1 11 -> nop, shift 3. 0010 1111 1100 1

01 -> add 4a. 0010 + 0010 0001 1100 1 shift 0000 1110 0 done 4b. 0010 shift P (sign ext) CS152 Lec6.32 Booths Example (2 x 3) Operation Multiplicand 0. initial value 1a. P = P - m 0010 1110 0000 1101 0 + 1110 1110 1101 0 1b. 0010 1111 0110 1 + 0010

2a. Product 0001 0110 1 next? 10 -> sub shift P (sign ext) 01 -> add shift P 2b. 0010 0000 1011 0 + 1110 10 -> sub 3a. 0010 1110 1011 0 shift 3b. 4a 0010 1111 0101 1 1111 0101 1 11 -> nop shift 4b. 0010 1111 1010 1

done CS152 Lec6.33 Radix-4 Modified Booths Multiple representations Once admit new symbols (i.e. 1), can have multiple representations of a number: Current Bits Bit to the Right Explanation Example Recode 00 0 Middle of zeros 00 00 00 00 00 00 (0) 01 0 Single one 00 00 00 01 00 01 (1) 10 0

Begins run of 1s 00 01 11 10 00 10 (-2) 11 0 Begins run of 1s 00 01 11 11 00 01 (-1) 00 1 Ends run of 1s 00 00 11 11 00 01 (1) 01 1 Ends run of 1s 00 01 11 11 00 10 (2) 10 1 Isolated 0

00 11 10 11 00 01 (-1) 11 1 Middle of run 00 11 11 11 00 00 (0) CS152 Lec6.34 MIPS logical instructions Instruction Example Meaning and and $1,$2,$3 or or $1,$2,$3 xor xor $1,$2,$3 nor

nor $1,$2,$3 and immediate andi $1,$2,10 or immediate ori $1,$2,10 xor immediate xori $1, $2,10 shift left logical sll $1,$2,10 shift right logical srl $1,$2,10 shift right arithm. sra $1,$2,10 shift left logical sllv $1,$2,$3 shift right logical srlv $1,$2, $3 shift right arithm. srav $1,$2, $3 Comment $1 = $2 & $3 $1 = $2 | $3 $1 = $2 $3 $1 = ~($2 |$3) $1 = $2 & 10 $1 = $2 | 10 $1 = ~$2 &~10 $1 = $2 << 10 $1 = $2 >> 10 $1 = $2 >> 10 $1 = $2 << $3 $1 = $2 >> $3 $1 = $2 >> $3 3 reg. operands; Logical AND 3 reg. operands; Logical OR 3 reg. operands; Logical XOR 3 reg. operands; Logical NOR Logical AND reg, constant Logical OR reg, constant Logical XOR reg, constant Shift left by constant Shift right by constant Shift right (sign extend) Shift left by variable Shift right by variable Shift right arith. by variable CS152 Lec6.35

Shifters Two kinds: logical-- value shifted in is always "0" "0" msb lsb "0" arithmetic-- on right shifts, sign extend msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! CS152 Lec6.36 Combinational Shifter from MUXes Basic Building Block sel A B 1 0 D 8-bit right shifter A7 A6 A5 A4 A3

A2 A1 S2 S1 S0 A0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

1 0 1 0 1 0 R7 R6 R5 R4 R3 R2 R1 R0 What comes in the MSBs? How many levels for 32-bit shifter? What if we use 4-1 Muxes ? CS152 Lec6.37 General Shift Right Scheme using 16 bit example S0 (0,1) S1 (0, 2) S2 (0, 4) S3 (0, 8)

If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs) CS152 Lec6.38 Funnel Shifter Instead Extract 32 bits of 64. Y X Shift Right Shift A by i bits (sa= shift right amount) Logical: Y = 0, X=A, sa=i R Y X 32 32 Arithmetic? Y = _, X=_, sa=_ Rotate? Y = _, X=_, sa=_ Shift Right 32 Left shifts? Y = _, X=_, sa=_ R CS152 Lec6.39 Barrel

Shifter Technology-dependent solutions: transistor per switch SR3 SR2 SR1 SR0 D3 D2 A6 D1 A5 D0 A4 A3 A2 A1 A0 CS152 Lec6.40 Summary Intro to VHDL a language to describe hardware - entity = symbol, architecture ~ schematic, signals = wires behavior can be higher level - x <= boolean_expression(A,B,C,D); Has time as concept Can activate when inputs change, not specifically invoked Inherently parallel Multiply: successive refinement to see final design 32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register

Booths algorithm to handle signed multiplies There are algorithms that calculate many bits of multiply per cycle (see exercises 4.36 to 4.39 in COD) Shifter: success refinement 1/bit at a time shift register to barrel shifter CS152 Lec6.41

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