A Back-End Design Flow for Single Chip Radios

A Back-End Design Flow for Single Chip Radios

Project Poster Presentation
EECS 141 SPRING 04

My Poster Title
My Name

Prof. Jan M. Rabaey

Outstanding Features of My Design
This poster shows the fastest array divider design in the world.
These ground-breaking results are products from the following
outstanding features we introduced:
A divider architecture that accomplishes faster than light propagation
The master job accomplished in critical path optimization using unheard of
mathematical algorithms

Summary of main results
Critical Path Delay

Estimated Area

Poster presentation should include the following
materials:
Schematic and functional verification
Divider architecture with clear explanation of your design methodology
Picture of the divider schematic
IRSIM (or HSPICE) simulation waveforms of quotient and remainder outputs

Critical path delay optimization
Block diagram of the critical path with gate-level schematics of most important
circuits
Critical path sizing methodology and results of sizing for minimum delay
SPICE simulation waveforms of quotient and remainder output, with critical path
delay annotated clearly. Identify your worst-case input operands.

Layout of critical cell and divider floorplan
Must include relative placement of the cells and the signal routing strategy
(including supply rails)

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